Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 9; pp. 1920 - 1930
• Main Authors: Chang-Joon Park, Onabajo, Marvin, Geddada, Hemasundar Mohan, Karsilayan, Aydin Ilker, Silva-Martinez, Jose
• Format: Journal Article
• Language: English
• Published: IEEE 01.09.2015
• Subjects: Ash; Capacitance; Current-mode adder; feed-forward (FF) sigma-delta modulators; flash analog-to-digital converter (ADC); Gain; low-power circuit design; Modulation; process-voltage-temperature (PVT) variation; quantizer; Radio frequency; summing stage; Transconductance; Transistors; tunable circuits; Current-mode adder; summing stage; quantizer; feed-forward (FF) sigma–delta modulators; tunable circuits; process-voltage-temperature (PVT) variation; flash analog-to-digital converter (ADC); low-power circuit design
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2353058

A 3-bit current-mode flash quantizer with current summing stage in a commercial 90-nm CMOS technology is presented. The topology is intended for low-power feed-forward continuous-time sigma-delta modulators. Current summation is realized using a common-gate structure. Replicas of the input signal current are compared with the reference currents through high-impedance nodes that ease the signal quantization. The comparison stage employs reset switches to enable fast comparisons. The proposed approach involves zero crossing comparators, and it employs current references instead of voltage references that demand a power-hungry resistive ladder. Results show that the proposed current-mode approach is faster than the conventional voltage-mode flash approach, and it requires a smaller input capacitance while consuming 53% less power. A 3-bit prototype design has a measured effective number of bits over 2.6 bits up to 2-GHz clock frequency with 10-MHz full-scale input signal. At 1.48-GHz clock frequency, the static differential nonlinearity (DNL) and integral nonlinearity (INL) errors are within -0.206 least significant bit (LSB) and 0.206 LSB, respectively. The proposed current-mode flash analog-to-digital converter (ADC) core dissipates 3.34-mW analog power from a 1.2 V supply while operating at 1.48 GHz. The core area of the ADC including the biasing circuitry is 0.0276 mm 2 .