A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering

• Published in: IEEE transactions on image processing Vol. 20; no. 11; pp. 3231 - 3241
• Main Authors: TSENG, Yu-Cheng, HSU, Po-Hsiung, CHANG, Tian-Sheuan
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Applied sciences; Architecture; Bandwidth; Bilateral filtering (BF); Complexity; Computation; Computational complexity; Convolution; Cost engineering; Detection, estimation, filtering, equalization, prediction; Exact sciences and technology; Filtering; Filtration; Histograms; Image processing; Information, signal and communications theory; integral histogram (IH); Kernel; Pixel; Reduction; Signal and communications theory; Signal processing; Signal, noise; Telecommunications and information theory; very-large-scale-integration (VLSI) design; Histogram; very-large-scale-integration (VLSI) design; VLSI circuit; Filtering; Scalability; Information rate; Bilateral filtering (BF); integral histogram (IH); Computational complexity; Information transmission
• ISSN: 1057-7149; 1941-0042
• DOI: 10.1109/TIP.2011.2159226

This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.