A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET

• Published in: IEEE solid-state circuits letters Vol. 3; pp. 174 - 177
• Main Authors: Tsai, Tsung-Hsien, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny Cheng-Hsiang, Staszewski, Robert Bogdan
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-digital PLL (ADPLL); Charge pumps; charge-pump PLL (CP-PLL); CMOS; fast settling; Frequency drift; hybrid PLL; Jitter; Measurement; Phase detectors; Phase locked loops; Quantization (signal); Realignment; realignment and injection locking; reference spur; Settling; Switches; Tuning; Vibration; Voltage-controlled oscillators
• ISSN: 2573-9603; 2573-9603
• DOI: 10.1109/LSSC.2020.3010278

All-digital PLLs (ADPLLs) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLLs) do not exhibit quantization noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain to cover frequency drift due to temperature variations. Further, in CP-PLLs, the reset pulse of phase detector (PD) must be wide for proper PLL functioning, but this sets a lower limit on reference spurs. We propose a hybrid-PLL in a 7-nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL. We introduce periodical phase realignment by the reference clock, and ultrashort pulse for resetting the PD. The hybrid PLL covers 0.2-4 GHz and settles in 0.6 us. It emits low −52 dB reference spurs in the conventional mode, and 1.05 ps and 0.62 ps integrated jitter in the conventional and realignment modes, respectively.