A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

• Published in: IEEE Communications surveys and tutorials Vol. 24; no. 1; pp. 524 - 556
• Main Authors: Ferraz, Oscar, Subramaniyan, Srinivasan, Chinthala, Ramesh, Andrade, Joao, Cavallaro, Joseph R., Nandy, Soumitra K., Silva, Vitor, Zhang, Xinmiao, Purnaprajna, Madhura, Falcao, Gabriel
• Format: Journal Article
• Language: English
• Published: IEEE 01.01.2022
• Subjects: ASIC; Computer architecture; Decoding; Error correction codes; error-correcting codes; Field programmable gate arrays; FPGA; GPU; Graphics processing units; non-binary LDPC decoders; Non-binary low-density parity-check codes; resilient communications; Throughput; Tutorials
• ISSN: 2373-745X
• DOI: 10.1109/COMST.2021.3126127

Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.