Low-Stress CMOS-Compatible Silicon Carbide Surface-Micromachining Technology-Part I: Process Development and Characterization
A low-temperature (<; 300 °C) low-stress microelectromechanical systems fabrication process based on a silicon carbide structural layer is presented. A partially conductive sintered target enables low-temperature dc sputtering of amorphous silicon carbide (SiC) at high deposition rates (75 nm/min...
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Published in | Journal of microelectromechanical systems Vol. 20; no. 3; pp. 720 - 729 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.06.2011
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | A low-temperature (<; 300 °C) low-stress microelectromechanical systems fabrication process based on a silicon carbide structural layer is presented. A partially conductive sintered target enables low-temperature dc sputtering of amorphous silicon carbide (SiC) at high deposition rates (75 nm/min). The low stress of the structural film allows for mechanically reliable structures to be fabricated, while the low-temperature deposition allows for pre-SiC metallization. The process is designed for low-cost film deposition and for complementary metal-oxide-semiconductor postintegration, stemming from chemical and thermal compatibility. Process flow, deposition, etching, and stress control are discussed, and a detailed process characterization is reported. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 1057-7157 1941-0158 |
DOI: | 10.1109/JMEMS.2011.2111355 |