Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI

• Published in: IEEE transactions on nanotechnology Vol. 17; no. 6; pp. 1259 - 1269
• Main Authors: Hills, Gage, Bardon, Marie Garcia, Doornbos, Gerben, Yakimets, Dmitry, Schuddinck, Pieter, Baert, Rogier, Doyoung Jang, Mattii, Luca, Sherazi, Syed Muhammed Yasser, Rodopoulos, Dimitrios, Ritzenthaler, Romain, Chi-Shuen Lee, Thean, Aaron Voon-Yew, Radu, Iuliana, Spessot, Alessio, Debacker, Peter, Catthoor, Francky, Raghavan, Praveen, Shulaker, Max M., Wong, H.-S Philip, Mitra, Subhasish
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance; Carbon nanotube (CNT); carbon nanotube field-effect transistor (CNFET); Carbon nanotubes; CNTFETs; Contact resistance; Energy efficiency; Energy management; energy-efficient digital very-large-scale integrated (VLSI) circuits; Field effect transistors; FinFETs; Integrated circuits; Leakage current; Logic circuits; Logic gates; Microprocessors; Nanowires; Nodes; Parasitics (electronics); Power efficiency; Power management; Semiconductor devices; Silicon germanides; Transistors; Very large scale integration
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2018.2871841

Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (~3× faster while simultaneously consuming ~3× less energy) compared to Si/SiGe FinFET. The ATOs provide <;50% EDP benefits. All analyses are performed at the same off-state leakage current density (≤100 nA per micron of FET width) and power density (≤100 W/cm 2 of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to 6.0× EDP benefit (versus Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length.