Point-to-point connectivity between neuromorphic chips using address events

• Published in: IEEE transactions on circuits and systems. 2, Analog and digital signal processing Vol. 47; no. 5; pp. 416 - 434
• Main Author: Boahen, K.A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bandwidth; Communication channels; Decoding; Design methodology; Neuromorphics; Neurons; Organizing; Throughput; Timing; Very large scale integration
• ISSN: 1057-7130; 1558-125X
• DOI: 10.1109/82.842110

This paper discusses connectivity between neuromorphic chips, which use the timing of fixed-height fixed-width pulses to encode information. Address-events (log/sub 2/(N)-bit packets that uniquely identify one of N neurons) are used to transmit these pulses in real time on a random-access time-multiplexed communication channel. Activity is assumed to consist of neuronal ensembles-spikes clustered in space and in time. This paper quantifies tradeoffs faced in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice. The arbitered channel is implemented with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, it is shown how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to /spl radic/N) by organizing neurons into rows and columns, and reduced in time (from log/sub 2/(N) to 2) by exploiting locality in the arbiter tree and in the row-column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog-digital systems are described.