A Loop Gain Optimization Technique for Integer- N TDC-Based Phase-Locked Loops

This paper presents a loop gain optimization technique for integer- N digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter performance, taking into account external and interna...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 62; no. 7; pp. 1873 - 1882
Main Authors Kuan, Ting-Kuei, Liu, Shen-Iuan
Format Journal Article
LanguageEnglish
Published IEEE 01.07.2015
Subjects
Clocks
Digital phase-locked loop
discrete-time domain analysis
Jitter
jitter minimization
loop gain optimization
loop latency
Noise
Optimization
Phase locked loops
Quantization (signal)
stability
time-to-digital converter
Timing
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Summary:This paper presents a loop gain optimization technique for integer- N digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the loop gain optimization technique, the digital phase-locked loops can automatically attain this loop gain in background to minimize the jitter. Theoretical analysis is presented. The stability issue and the impact of loop latency are also discussed. Finally, the analysis is compared to behavioral simulations with good agreement.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2015.2423793