Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost

Field-programmable gate array (FPGA) is a promising technology for the implementing of high-performance and power-efficient cloud computing by serving dedicated hardware as co-processor to accelerate loads on CPUs. However, developing an FPGA-based system is challenging because the complexity of the...

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Bibliographic Details
Published inIPSJ Transactions on System LSI Design Methodology Vol. 10; pp. 63 - 70
Main Authors Zhao, Qian, Amagasaki, Motoki, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
Format Journal Article
LanguageEnglish
Published Tokyo Information Processing Society of Japan 2017
Japan Science and Technology Agency
Subjects
Accelerators
Central processing units
Cloud computing
Co-design
CPUs
Downloading
Field programmable gate arrays
FPGA
Hardware
hardware acceleration
Microprocessors
open-source hardware
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Summary:Field-programmable gate array (FPGA) is a promising technology for the implementing of high-performance and power-efficient cloud computing by serving dedicated hardware as co-processor to accelerate loads on CPUs. However, developing an FPGA-based system is challenging because the complexity of the hardware and software co-design. In this paper, we propose a platform named hCODE to simplify the design, share, and deployment of FPGA accelerators. First, we adopt a shell-and-IP design pattern to improve the reusability and the portability of accelerator designs. Second, we implement an open accelerator repository to bridge hardware development and software development on one platform. On the hCODE platform, hardware developers can provide designs that follow hCODE specifications, which allowing software engineers to easily search, download, and integrate accelerators in their applications without caring about the hardware details.
ISSN:1882-6687
1882-6687
DOI:10.2197/ipsjtsldm.10.63