Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays

In this letter, the write disturb of Hf 0.5 Zr 0.5 O 2 -based 1T-FeFET nonvolatile AND memory array is experimentally investigated for <inline-formula> <tex-math notation="LaTeX">{V}_{W} </tex-math></inline-formula>/2 and <inline-formula> <tex-math notation...

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Bibliographic Details
Published inIEEE electron device letters Vol. 39; no. 11; pp. 1656 - 1659
Main Authors Ni, Kai, Li, Xueqing, Smith, Jeffrey A., Jerry, Matthew, Datta, Suman
Format Journal Article
LanguageEnglish
Published New York IEEE 01.11.2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:In this letter, the write disturb of Hf 0.5 Zr 0.5 O 2 -based 1T-FeFET nonvolatile AND memory array is experimentally investigated for <inline-formula> <tex-math notation="LaTeX">{V}_{W} </tex-math></inline-formula>/2 and <inline-formula> <tex-math notation="LaTeX">{V}_{W} </tex-math></inline-formula>/3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low-<inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} </tex-math></inline-formula> erased state and the increased read current of the high-<inline-formula> <tex-math notation="LaTeX">{V}_{\textsf {TH}} </tex-math></inline-formula> programmed state are the key factors that limit the maximum array size.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2018.2872347