The impact of iron, copper, and calcium contamination of silicon surfaces on the yield of a MOS DRAM test process

The impact of the silicon surface contaminants iron, copper and calcium on gate oxide integrity was investigated quantitatively by evaluating MOS test capacitors built on intentionally contaminated wafers. All three elements influenced dielectric breakdown field strength and charge to breakdown valu...

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Bibliographic Details
Published inSolid-state electronics Vol. 41; no. 7; pp. 1021 - 1025
Main Authors Burte, E.P, Aderhold, W
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.07.1997
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Summary:The impact of the silicon surface contaminants iron, copper and calcium on gate oxide integrity was investigated quantitatively by evaluating MOS test capacitors built on intentionally contaminated wafers. All three elements influenced dielectric breakdown field strength and charge to breakdown values if the surface contamination level was raised beyond 10 9 to 10 10 atoms/cm 2. The distribution of these elements in the silicon oxide could be related to electrical yield measurements.
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ISSN:0038-1101
1879-2405
DOI:10.1016/S0038-1101(97)00016-6