Comprehensive numerical simulation of threshold-voltage transients in nitride memories

• Published in: Solid-state electronics Vol. 56; no. 1; pp. 23 - 30
• Main Authors: Mauri, Aurelio, Amoroso, Salvatore M., Monzio Compagnoni, Christian, Maconi, Alessandro, Spinelli, Alessandro S.
• Format: Journal Article
• Language: English
• Published: Kidlington Elsevier Ltd 01.02.2011; Elsevier
• Subjects: Applied sciences; Charge-trap memories; Data storage; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Gates; Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; Mathematical analysis; Mathematical models; Memory devices; Nitrides; Non volatile memories; Semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Storage and reproduction of information; Trapping; Tunneling; Semiconductor device modeling; Tunneling; Non volatile memories; Charge-trap memories; Voltage threshold; Memory devices; Tunnel effect; Self consistency; Transistor gate; Multiple layer; Erasure; Modeling; Addressing; Optimization; Semiconductor device; Continuity equation; Non volatile memory; Integrated circuit; Numerical simulation; Drift mobility; Charge-trapping memory
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2010.11.004

► We present a complete model to describe charge trap devices behavior. ► In this study any mathematical aspect regarding holes and electrons is detailed modeled. ► Experimental data coming from different TANOS and SONOS devices are correctly reproduced. This paper presents a comprehensive numerical modeling for the threshold-voltage transients of nitride-based memory devices during programming, erasing and data retention. The developed numerical tool self-consistently solves the Poisson, continuity and trapping equations in the nitride layer using a drift-diffusion formalism. The continuity equation has been discretized using the Scharfetter–Gummel scheme and a modified Gummel-map has been optimized to ensure fully convergence of the equations. The numerical model is able to describe the memory device operation for different gate bias regimes, therefore addressing both the program/erase and the retention conditions. Finally, numerical results are shown to carefully reproduce experimental data on template devices with different gate stack compositions, validating the physical assumptions and making the model a valuable tool for nitride memories investigation and design.