A novel buffering fault‐tolerance approach for network on chip (NoC)

Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that...

Full description

Saved in:
Bibliographic Details
Published inIET circuits, devices & systems Vol. 17; no. 4; pp. 250 - 257
Main Authors Jafarzadeh, Nima, Jalili, Ahmad, Alzubi, Jafar A., Rezaee, Khosro, Liu, Yang, Gheisari, Mehdi, Sadeghi Bigham, Bahram, Javadpour, Amir
Format Journal Article
LanguageEnglish
Published Stevenage John Wiley & Sons, Inc 01.07.2023
Wiley
Subjects
Algorithms
Bandwidths
buffering
Buffers
Communication
Critical point
Design
Error analysis
Error correction & detection
error injection
Failure
Fault tolerance
Gossip
integrated circuit reliability
Integrated circuits
microprocessor chips
Multiprocessing
network on chip (NoC)
network‐on‐chip
Performance evaluation
router
Routers
Subsystems
System on chip
Traffic
Trouble shooting
virtual channel
Online AccessGet full text

Cover

More Information
Summary:Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance is proposed, which uses the existing resources efficiently. So, it does not impose any overhead on hardware and improves the error tolerance scale. The authors also evaluate it from different perspectives to show its superior performance.
ISSN:1751-858X
1751-8598
DOI:10.1049/cds2.12127