Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 39; no. 2; pp. 424 - 437
• Main Authors: Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-Sun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Accelerators; Algorithms; Artificial neural networks; Compilers; Convolution; Convolutional neural networks (CNNs); Field programmable gate arrays; FPGA; Hardware; Inference; Kernel; Modules; Network topologies; neural network hardware; Optimization; Prototyping; Schedules
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2018.2884972

A broad range of applications are increasingly benefiting from the rapid and flourishing development of convolutional neural networks (CNNs). The FPGA-based CNN inference accelerator is gaining popularity due to its high-performance and low-power as well as FPGA's conventional advantage of reconfigurability and flexibility. Without a general compiler to automate the implementation, however, significant efforts and expertise are still required to customize the design for each CNN model. In this paper, we present an register-transfer level (RTL)-level CNN compiler that automatically generates customized FPGA hardware for the inference tasks of various CNNs, in order to enable high-level fast prototyping of CNNs from software to FPGA and still keep the benefits of low-level hardware optimization. First, a general-purpose library of RTL modules is developed to model different operations at each layer. The integration and dataflow of physical modules are predefined in the top-level system template and reconfigured during compilation for a given CNN algorithm. The runtime control of layer-by-layer sequential computation is managed by the proposed execution schedule so that even highly irregular and complex network topology, e.g., GoogLeNet and ResNet, can be compiled. The proposed methodology is demonstrated with various CNN algorithms, e.g., NiN, VGG, GoogLeNet, and ResNet, on two standalone Intel FPGAs, Arria 10, and Stratix 10, achieving end-to-end inference throughputs of 969 GOPS and 1604 GOPS, respectively, with batch size of one.