Multiple integration method for a high signal-to-noise ratio readout integrated circuit

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 52; no. 9; pp. 553 - 557
• Main Authors: Kang, Sang Gu, Woo, Doo Hyung, Lee, Hee Chul
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2005; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Application specific integrated circuits; Capacitance; Capacitors; Circuit noise; Costs; Infrared detectors; Infrared focal plane arrays (IR FPAs); readout integrated circuit; Signal resolution; Signal to noise ratio; signal-to-noise ratio (SNR); Timing; Voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2005.848984

A multiple integration method is reported that greatly improves the signal-to-noise ratio (SNR) for applications with a high-resolution infrared (IR) focal plane array. The signal from each pixel is repeatedly sampled into an integration capacitor and then output and summed into an outside memory that continues for n read cycles during each period of a frame. This method increases the effective capacity of the charge integration and improves sensitivity. Because a low-noise function block and high-speed operation of the readout circuit is required, a new concept is proposed that enables the readout circuit to perform digitization by a voltage skimming method. The readout circuit was fabricated using a 0.6-/spl mu/m CMOS process for a 64/spl times/64 midwavelength IR HgCdTe detector array. The readout circuit effectively increases the charge storage capacity to 2.4/spl times/10/sup 8/ electrons and then provides a greatly improved SNR by a factor of approximately 3.