Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

• Published in: IEEE journal of the Electron Devices Society Vol. 10; pp. 35 - 39
• Main Authors: Gu, Jie, Zhang, Qingzhu, Wu, Zhenhua, Luo, Yanna, Cao, Lei, Cai, Yuwei, Yao, Jiaxin, Zhang, Zhaohao, Xu, Gaobo, Yin, Huaxiang, Luo, Jun, Wang, Wenwu
• Format: Journal Article
• Language: English
• Published: New York IEEE 2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Current density; Doping; Etching; Field effect transistors; FinFETs; Gallium arsenide; gate-all-around (GAA); Ground plane; Logic gates; Nanosheet FET; Nanosheets; Optimization; parasitic channel; Semiconductor devices; sub-fin; Three-dimensional displays; Transistors
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2021.3130123

A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio (<inline-formula> <tex-math notation="LaTeX">\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}} </tex-math></inline-formula>) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.