Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

• Published in: IEEE journal of the Electron Devices Society Vol. 8; pp. 336 - 340
• Main Authors: Cheng, Weijun, Liang, Renrong, Xu, Gaobo, Yu, Guofang, Zhang, Shuqin, Yin, Huaxiang, Zhao, Chao, Ren, Tian-Ling, Xu, Jun
• Format: Journal Article
• Language: English
• Published: New York IEEE 2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arsenic; Cryogenic temperature; Germanium; Implantation; line tunneling; Logic gates; Low temperature; Room temperature; Silicon; Temperature; Temperature measurement; TFET Ge PAI; TFETs; Transconductance; Tunneling
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2020.2981974

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of <inline-formula> <tex-math notation="LaTeX">40 \mu \text{A}/\mu \text{m} </tex-math></inline-formula>, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with <inline-formula> <tex-math notation="LaTeX">\text{V}_{\mathrm{ DS}} =\,\,\text{V}_{\mathrm{ GS}}=1 </tex-math></inline-formula> V at room temperature. It is shown that once the trap assisted tunneling is suppressedat the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decadewas obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application.