Automated High-Level Generation of Low-Power Approximate Computing Circuits

• Published in: IEEE transactions on emerging topics in computing Vol. 7; no. 1; pp. 18 - 30
• Main Authors: Nepal, Kumud, Hashemi, Soheil, Tann, Hokchhay, Bahar, R. Iris, Reda, Sherief
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Algorithm design and analysis; Approximate computing; Approximation algorithms; Arithmetic; Artificial intelligence; Circuit design; Computer graphics; Computer vision; critical path optimization; design space exploration; Design standards; Domains; Image processing; Logic gates; low area circuits; low power circuits; Machine learning; Operators; Parallel processing; Power consumption; Power demand; Signal processing; Signal processing algorithms; Space exploration; Transformations; voltage scaling
• ISSN: 2168-6750; 2168-6750
• DOI: 10.1109/TETC.2016.2598283

Numerous application domains (e.g., signal and image processing, computer graphics, computer vision, and machine learning) are inherently error tolerant, which can be exploited to produce approximate ASIC implementations with low power consumption at the expense of negligible or small reductions in application quality. A major challenge is the need for approximate and high-level design generation tools that can automatically work on arbitrary designs. In this article, we provide an expanded and improved treatment of our ABACUS methodology, which aims to automatically generate approximate designs directly from their behavioral register-transfer level (RTL) descriptions, enabling a wider range of possible approximations. ABACUS starts by creating an abstract syntax tree (AST) from the input behavioral RTL description of a circuit, and then applies variant operators to the AST to create acceptable approximate designs. The devised variant operators include data type simplifications, arithmetic operation approximations, arithmetic expressions transformations, variable-to-constant substitutions, and loop transformations. A design space exploration technique is devised to explore the space of possible variant approximate designs and to identify the designs along the Pareto frontier that represents the trade-off between accuracy and power consumption. In addition, ABACUS prioritizes generating approximate designs that, when synthesized, lead to circuits with simplified critical paths, which are exploited to realize complementary power savings through standard voltage scaling. We integrate ABACUS with a standard ASIC design flow, and evaluate it on four realistic benchmarks from three different domains-machine learning, signal processing, and computer vision. Our tool automatically generates many approximate design variants with large power savings, while maintaining good accuracy. We demonstrate the scalability of ABACUS by parallelizing the flow and use of recent standard synthesis tools. Compared to our previous efforts, the new ABACUS tool provides up to 20.5× speed-up in runtime, while able to generate approximate circuits that lead to additional power savings reaching up to 40 percent.