Progress in a novel architecture for high performance processing

• Published in: Japanese Journal of Applied Physics Vol. 57; no. 4S; pp. 4 - 11
• Main Authors: Zhang, Zhiwei, Liu, Meng, Liu, Zijun, Du, Xueliang, Xie, Shaolin, Ma, Hong, Ding, Guangxin, Ren, Weili, Zhou, Fabiao, Sun, Wenqin, Wang, Huijuan, Wang, Donglin
• Format: Journal Article
• Language: English
• Published: Tokyo The Japan Society of Applied Physics 01.04.2018; Japanese Journal of Applied Physics
• Subjects: Application specific integrated circuits; Central processing units; Computer architecture; Computing time; CPUs; Efficiency; Field effect transistors; Graphics processing units; Integrated circuits; Machine learning; Power efficiency; Semiconductor devices; Semiconductors; Wireless communications
• ISSN: 0021-4922; 1347-4065
• DOI: 10.7567/JJAP.57.04FA03

The high performance processing (HPP) is an innovative architecture which targets on high performance computing with excellent power efficiency and computing performance. It is suitable for data intensive applications like supercomputing, machine learning and wireless communication. An example chip with four application-specific integrated circuit (ASIC) cores which is the first generation of HPP cores has been taped out successfully under Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm low power process. The innovative architecture shows great energy efficiency over the traditional central processing unit (CPU) and general-purpose computing on graphics processing units (GPGPU). Compared with MaPU, HPP has made great improvement in architecture. The chip with 32 HPP cores is being developed under TSMC 16 nm field effect transistor (FFC) technology process and is planed to use commercially. The peak performance of this chip can reach 4.3 teraFLOPS (TFLOPS) and its power efficiency is up to 89.5 gigaFLOPS per watt (GFLOPS/W).