Incorporating yield enhancement into the floorplanning process

The traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that, for certain types of chips, the floorplan can affect the yiel...

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Bibliographic Details
Published inIEEE transactions on computers Vol. 49; no. 6; pp. 532 - 541
Main Authors Koren, I., Koren, Z.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.06.2000
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Algorithms
Chips
Circuit faults
Cost engineering
Cost function
Decoding
Floorplans
Integrated circuit interconnections
Integrated circuit yield
Manufacturing
Microprocessors
Minimization
Optimization
Routing
Tradeoffs
Wire
Wiring
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Summary:The traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that, for certain types of chips, the floorplan can affect the yield of the chip as well. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a floorplan. The goal of this paper is to investigate the two seemingly unrelated, and often conflicting, objectives of yield enhancement and routing complexity minimization. We analyze the possible trade-offs between the two and then present a constructive algorithm for incorporating yield enhancement as a secondary objective into the floorplanning process, with the main objective still being the minimization of the overall routing costs.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9340
1557-9956
DOI:10.1109/12.862213