PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits

• Published in: IEEE transactions on applied superconductivity Vol. 29; no. 4; pp. 1 - 14
• Main Authors: Pasandi, Ghasem, Pedram, Massoud
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Binary trees; Boolean algebra; Clocks; CMOS; CMOS technology; Delays; Dynamic programming; Energy efficient; energy-efficient rapid single flux quantum (ERSFQ); energy-efficient SFQ (eSFQ); Josephson junctions; Logic circuits; Logic gates; Logic programming; logic synthesis; low power; Mapping; Power transmission lines; RSFQ; SFQ; State of the art; superconducting electronics; technology mapping
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/TASC.2018.2880343

This paper presents a path balancing technology mapping algorithm, which is a new algorithm for generating a mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing technology mapping is required in dc-biased single flux quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing technology mapping, which generates optimal solutions for dc-biased SFQ (e.g., rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general directed acyclic graph structure. Experimental results show that our path balancing technology mapper reduces the balancing overhead by up to 2.7 × and with an average of 21% compared to the state-of-the-art academic technology mappers.