Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

• Published in: IEEE journal of the Electron Devices Society Vol. 8; pp. 724 - 730
• Main Authors: Ma, William Cheng-Yu, Huang, Yan-Jia, Chen, Po-Jen, Jhu, Jhe-Wei, Chang, Yan-Shiuan, Chang, Ting-Hsuan
• Format: Journal Article
• Language: English
• Published: New York IEEE 2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Etching; Fabrication; Integrated circuits; Lithography; Logic gates; low power; Monolithic 3D-IC; nanosheet channel; Performance degradation; Polysilicon; Semiconductor devices; Silicon; Thin film transistors; thin-film transistor; Threshold voltage

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) struc...