Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

• Published in: IEEE journal of the Electron Devices Society Vol. 8; pp. 724 - 730
• Main Authors: Ma, William Cheng-Yu, Huang, Yan-Jia, Chen, Po-Jen, Jhu, Jhe-Wei, Chang, Yan-Shiuan, Chang, Ting-Hsuan
• Format: Journal Article
• Language: English
• Published: New York IEEE 2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Etching; Fabrication; Integrated circuits; Lithography; Logic gates; low power; Monolithic 3D-IC; nanosheet channel; Performance degradation; Polysilicon; Semiconductor devices; Silicon; Thin film transistors; thin-film transistor; Threshold voltage
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2020.3009350

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 10 7 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 mA. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology.