Wafer-level chip size package (WL-CSP)

• Published in: IEEE transactions on advanced packaging Vol. 23; no. 2; pp. 233 - 238
• Main Authors: Topper, M., Fehlberg, S., Scherpinski, K., Karduck, C., Glaw, V., Heinricht, K., Coskina, P., Ehrmann, O., Reichl, H.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Piscataway, NY IEEE 01.05.2000; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Assembly; Chip scale packaging; Chips; Cost engineering; Design. Technologies. Operation analysis. Testing; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronic systems; Electronics; Electronics packaging; Exact sciences and technology; Integrated circuit packaging; Integrated circuit technology; Integrated circuits; Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology; Optimization; Packages; Packaging; Plastic packaging; Printed circuits; Production; Semiconductor device packaging; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Size reduction; Wafer scale integration; Reliability; Chip; Technology; Electronic packaging; Integrated circuit
• ISSN: 1521-3323; 1557-9980
• DOI: 10.1109/6040.846640

Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost.