Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 20; no. 3; pp. 437 - 448
• Main Authors: Nunez-Yanez, J. L., Nabina, A., Hung, E., Vafiadis, G.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Applied sciences; Blocking; Circuit properties; Cogeneration; Complexity theory; Computer architecture; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Field-programmable gate array (FPGA); H.264; Hardware; Integrated circuits; Integrated circuits by function (including memories and processors); Motion estimation; Optimization; Pixel; Processors; Program processors; reconfigurable processor; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Studies; Very large scale integration; video coding; Performance evaluation; High resolution; Processor; Motion estimation; Scalability; Instruction sets; Cogeneration; Image processing; H.264; Field programmable gate array; video coding; reconfigurable processor; Implementation; Optimization; Block matching; Codec; Field-programmable gate array (FPGA); Coding; Integrated circuit; Reconfigurable architectures; Fast algorithm
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2010.2104166

This paper presents a flexible and scalable motion estimation processor capable of supporting the processing requirements for high-definition (HD) video using the H.264 Advanced Video Codec, which is suited for FPGA implementation. Unlike most previous work, our core is optimized to execute all existing fast block matching algorithms, which we show to match or exceed the inter-frame prediction performance of traditional full-search approaches at the HD resolutions commonly in use today. Using our development tools, such algorithms can be described using a C-style syntax which is compiled into our custom instruction set. We show that different HD sequences exhibit different characteristics which necessitate a flexible and configurable solution when targeting embedded applications. This is supported in our core and toolset by allowing designers to modify the number of functional units to be instantiated. All processor instances remain binary compatible so recompilation of the motion estimation algorithm is not required. Due to this optimization process, it is possible to match the processing requirements of the selected motion estimation algorithm to the hardware microarchitecture leading to a very efficient implementation.