A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology

• Published in: IEEE journal of solid-state circuits Vol. 51; no. 12; pp. 3005 - 3019
• Main Authors: Yan Zhao, Zuow-Zun Chen, Yuan Du, Yilei Li, Al Hadi, Richard, Virbila, Gabriel, Yinuo Xu, Yanghyo Kim, Tang, Adrian, Reck, Theodore J., Chang, Mau-Chung Frank
• Format: Journal Article
• Language: English
• Published: IEEE 01.12.2016
• Subjects: Bulk voltage tuning; Couplings; Frequency conversion; frequency synthesizer; Frequency synthesizers; harmonic oscillator; injection locking; Instruments; Phase noise; phase-locked loop (PLL); subsampling phase detector; terahertz; triple-push Colpitts oscillator (TPCO); triple-push oscillator (TPO); Voltage-controlled oscillators
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2016.2601614

This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.