Area‐ and energy‐efficient high‐throughput QC‐LDPC encoder for space applications

• Published in: Electronics letters Vol. 59; no. 23
• Main Authors: Li, Lintao, Lv, Jiayi, Li, Yimin
• Format: Journal Article
• Language: English
• Published: Stevenage John Wiley & Sons, Inc 01.12.2023; Wiley
• Subjects: Algorithms; channel coding; circuits and systems; CMOS; Coders; Codes; Coding; Data systems; encoding; Energy consumption; Energy utilization; Field programmable gate arrays; Low density parity check codes; Parity; Satellite communications
• ISSN: 0013-5194; 1350-911X
• DOI: 10.1049/ell2.13047

An area‐ and energy‐efficient encoding method and encoder architecture are proposed for the quasi‐cyclic low‐density parity check (LDPC) in near‐earth applications recommended by the Consultant Committee for Space Data Systems. The proposed encoding method reduces the computational complexity using a switch network before bit XOR operations in vector–matrix multiplication. A fully parallel LDPC encoder is implemented on the Taiwan Semiconductor Manufacturing Company 90 nm complementary metal oxide semiconductor (CMOS) technology, achieving a throughput of 10.06 Tbps with the lower area and energy utilization. An area‐ and energy‐efficient encoding method and encoder architecture are proposed using a bit selector before bit XOR operations in vector–matrix multiplication. A fully parallel low‐density parity check encoder is implemented on the aiwan Semiconductor Manufacturing Company (TSMC) 90 nm complementary metal oxide semiconductor (CMOS) technology, achieving a throughput of 10.06 Tbps with the lower area and energy utilization.