Improvement of P--N Junction Leakage and Reduction in Interface State Density in Transistors by Cryo Implantation Technology

Cryo implantation by a rapid thermal annealing process was applied to achieve defect-free shallow junctions. Boron ions were implanted in (100) Si substrates cooled using liquid nitrogen, with temperature controlled at $-160$ °C or lower during ion implantation. It was found that an amorphous layer...

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Published inJapanese Journal of Applied Physics Vol. 52; no. 10; pp. 105501 - 105501-7
Main Authors Murakoshi, Atsushi, Iwase, Masao, Niiyama, Hiromi, Tomita, Mitsuhiro, Suguro, Kyoichi
Format Journal Article
LanguageEnglish
Published The Japan Society of Applied Physics 01.10.2013
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Summary:Cryo implantation by a rapid thermal annealing process was applied to achieve defect-free shallow junctions. Boron ions were implanted in (100) Si substrates cooled using liquid nitrogen, with temperature controlled at $-160$ °C or lower during ion implantation. It was found that an amorphous layer was formed by boron implantation and that the amorphous layer completely recovered to single crystals after annealing at 900 °C for 30 s. No dislocation was observed in the implanted layer. It was also found that the thermal diffusion of boron was suppressed by cryo implantation. Furthermore, cryo implantation was found to be very effective in reducing the density of defects, and P--N junction leakage was reduced by one order of magnitude compared with that in the case of room temperature implantation. These results suggest that the transient enhanced diffusion of boron can be reduced by suppressing vacancy migration toward the surface during implantation. Moreover, the substrate-cooling effect is very effective for improving surface roughness, and it is a very effective technology not only for reducing Si/SiO 2 interface state density but also for improving the reliability of gate oxide.
Bibliography:(Color online) SIMS depth profile of (100) Si substrates implanted with B at room temperature and $-160$ °C. B implantation dose: (a) $1\times 10^{13}$ cm -2 ; (b) $1\times 10^{15}$ cm -2 . (Color online) SIMS depth profile of (100) Si substrates implanted with B after annealing. B implantation dose: (a) $1\times 10^{13}$ cm -2 ; (b) $1\times 10^{15}$ cm -2 . (Color online) (a) Sheet resistance and (b) sheet carrier concentration as functions of annealing temperature. Cross-sectional TEM photographs of (100) Si substrate implanted with B at $-160$ °C. (a) As-implanted. (b) After annealing at 900 °C for 30 s. Cross-sectional TEM photographs of (100) Si substrate implanted with B at room temperature. (a) As-implanted. (b) After annealing at 900 °C for 30 s. (Color online) P--N junction leakage characteristics of Si substrate implanted with B at room temperature and $-160$ °C. B dose: (a) $1\times 10^{13}$ cm -2 ; (b) $1\times 10^{14}$ cm -2 ; (c) $1\times 10^{15}$ cm -2 . (Color online) AFM image of Si surface state after annealing at 900 °C for 30 s. (a) Room temperature; (b) $-160$ °C. (Color online) Cross-sectional structure mimetic diagram and process flow of MOS capacitors. (Color online) SILK characteristics of MOS capacitor. (a) Room temperature. (b) $-160$ °C. (Color online) Relationship between $\Delta E_{\text{g}}$ (stress leakage current of $1\times 10^{-8}$ A/cm 2 ) and EOT. Cross-sectional TEM photographs of Si/SiO 2 interface. (a) Room temperature. (b) $-160$ °C.
ObjectType-Article-1
SourceType-Scholarly Journals-1
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ISSN:0021-4922
1347-4065
DOI:10.7567/JJAP.52.105501