Folded gate LDMOS transistor with low on-resistance and high transconductance

• Published in: IEEE transactions on electron devices Vol. 48; no. 12; pp. 2917 - 2928
• Main Authors: Yuanzheng Zhu, Liang, Y.C., Shuming Xu, Pang-Dow Foo, Sin, J.K.O.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2001; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Channels; Density; Devices; Gates; MOSFETs; Semiconductor devices; Transconductance; Transistors; Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.974729

In this paper, a novel folded gate LDMOS transistor (FG-LDMOST) structure is proposed with the properties of low on-resistance and high transconductance. The FG structure is formed by adding a single trench process into the conventional LDMOS process. In this way, the channel density can be largely increased after the additional process. From the data by laboratory measurement, with the FG concept applied, the specific on-resistance of FG-LDMOS device is reduced by 45.66% compared to the conventional LDMOS structure with similar dimensions. At the same time, the transconductance value is improved by 64.09%. The capacitance and effective channel mobility for both FG-LDMOST and the counterpart are also measured and compared. The significance of the FG concept can also be applied in making CMOS and other MOS-gated devices in low to medium operating voltage ranges.