On designing sub-70-nm semiconductor materials and processes

• Published in: IEEE transactions on semiconductor manufacturing Vol. 15; no. 2; pp. 157 - 168
• Main Authors: Zhirnov, V.V., Cavin, R.K., Herr, D.J.C., Wooldridge, T.A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Atomic beams; Atomic layer deposition; CMOS technology; Devices; Dielectric materials; Fabrication; Lithography; Molecular beam epitaxy; Nanoscale devices; Optical sensors; Patterning; Remedies; Semiconductor materials; Semiconductors; Silicon
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/66.999587

In this paper, the authors examine salient materials and processing technologies that we believe are necessary to sustain the continued cadence of mainstream silicon technology. Specifically, they discuss the need for technologies that yield atomically smooth interfaces and suggest that perhaps molecular beam epitaxy has reached the point where it can transition into mainstream silicon manufacturing. Patterning candidates for next generation lithography are discussed and the possible role of maskless patterning technologies is considered. The role of doping on the performance of projected future generation devices is discussed and the tradeoffs involved in the precise control of the number and location of dopants for devices in the far nanometer regime are considered. ESH issues and possible remedies for future generation processes are also briefly discussed.