Extraction of geometry-related interconnect variation based on parasitic capacitance data

• Published in: IEEE electron device letters Vol. 35; no. 10; pp. 980 - 982
• Main Authors: Sun, Li-Jie, Shi, Yan-Ling, Cheng, Jia, Ren, Zheng, Shang, Gan-Bing, Hu, Shao-Jian, Chen, Shou-Mian, Zhao, Yu-Hang, Zhang, Long, Li, Xiao-Jin
• Format: Journal Article
• Language: English
• Published: IEEE 01.10.2014
• Subjects: charge-induced-injection error-free charge-based capacitance measurement (CIEF CBCM); Data mining; Geometric-related variation; Integrated circuit interconnections; interconnect parasitic extraction; Layout; Metals; non-overlapping signal generation circuitry; Parasitic capacitance; System-on-chip; Geometric-related variation; non-overlapping signal generation circuitry; charge-induced-injection error-free charge-based capacitance measurement (CIEF CBCM); interconnect parasitic extraction
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2014.2344173

A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with this optimized ITF. Meanwhile, an on-chip interconnect test technique with nonoverlapping signal generation circuitry based on charge-induced-injection error-free charge-based capacitance measurement has been designed in this letter to simplify the test procedure.