FLIP-Q: A QCIF Resolution Focal-Plane Array for Low-Power Image Processing

• Published in: IEEE journal of solid-state circuits Vol. 46; no. 3; pp. 669 - 680
• Main Authors: Fernández-Berni, J, Carmona-Galán, R, Carranza-González, L
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Arrays; Blocking; Chips; CMOS image sensors; Conversion; Design. Technologies. Operation analysis. Testing; Electronics; Energy resolution; Exact sciences and technology; focal-plane scale space; foveation; Gaussian; Image processing; Imaging devices; Integrated circuits; Integrated circuits by function (including memories and processors); low-power image processing; Microprocessors; multiresolution; Optoelectronic devices; Pixel; Representations; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; simplified scene representation; Spatial resolution; Transistors; Focal plane; Processor; Image processing; CMOS image sensors; Multiresolution analysis; foveation; AD converter; Integrated circuit testing; Complementary MOS technology; Electric power consumption; Parallel processing; multiresolution; Focal plane arrays; AD conversion; Rectangular shape; Readout electronics; Analog processing; low-power image processing; Interconnection; Integrated circuit; simplified scene representation; Miniaturization; Image sensor; Low-power electronics; focal-plane scale space
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2102591

This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power. The array is composed of pixel-level processing elements which carry out analog image processing concurrently with photosensing. These processing elements can be grouped into fully-programmable rectangular-shape areas by loading the appropriate interconnection patterns into the registers at the edge of the array. The targeted processing can be thus performed block-wise. Readout is done pixel-by-pixel in a random access fashion. On-chip 8b ADC is provided. The image processing primitives implemented by the chip, experimentally tested and fully functional, are scale space and Gaussian pyramid generation, fully-programmable multiresolution scene representation-including foveation-and block-wise energy-based scene representation. The power consumption associated to the capture, processing and A/D conversion of an image flow at 30 fps, with full-frame processing but reduced frame size output, ranges from 2.7 mW to 5.6 mW, depending on the operation to be performed.