Linear LMS Compensation for Timing Mismatch in Time-Interleaved ADCs
The time-interleaved architecture permits the implementation of high-frequency analog-to-digital converters (ADCs) by multiplexing the output of several time-shifted low-frequency ADCs. An issue in the design of a time-interleaved ADC is the compensation of timing mismatch, which is the difference b...
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Published in | IEEE transactions on circuits and systems. I, Regular papers Vol. 56; no. 11; pp. 2476 - 2486 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.11.2009
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | The time-interleaved architecture permits the implementation of high-frequency analog-to-digital converters (ADCs) by multiplexing the output of several time-shifted low-frequency ADCs. An issue in the design of a time-interleaved ADC is the compensation of timing mismatch, which is the difference between the ideal and real sampling instants. In this paper, we propose a compensation method that, as opposite to existing approaches, does not assume that the input signal is band limited but assumes instead that it has a stationary known power spectrum. The compensation is then designed in a statistically optimal sense. This largely reduces the compensation order required to achieve a given reconstruction accuracy. Also, under the band-limited assumption, the proposed method achieves perfect reconstruction if no constraints are imposed on the order of the compensation. Simulation results show that a rough estimate of the input spectrum can be used without much performance loss, showing that an accurate knowledge of the input spectrum is not necessarily required. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 1549-8328 1558-0806 |
DOI: | 10.1109/TCSI.2009.2015730 |