SMT layout overhead and scalability

• Published in: IEEE transactions on parallel and distributed systems Vol. 13; no. 2; pp. 142 - 155
• Main Authors: Burns, J., Gaudiot, J.-L.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Architecture; Chips; Gain; Hardware; Instruction sets; Microarchitecture; Microprocessors; Performance analysis; Performance evaluation; Scalability; Semiconductor devices; Silicon; Surface-mount technology; Throughput; Transistors
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/71.983942

Simultaneous Multi-Threading (SMT) is a hardware technique that increases processor throughput by issuing instructions simultaneously from multiple threads. However, while SMT can be added to an existing microarchitecture with relatively low overhead, this additional chip area could be used for other resources such as more functional units, larger caches, or better branch predictors. How large is the SMT overhead and at what point does SMT no longer pay off for maximum throughput compared to adding other architecture features? This paper evaluates the silicon overhead of SMT by performing a transistor/interconnect-level analysis of the layout. We discuss microarchitecture issues that impact SMT implementations and show how the Instruction Set Architecture (ISA) and microarchitecture can have a large effect on the SMT overhead and performance. Results show that SMT yields large performance gains with small to moderate area overhead.