Clock recovery based on packet inter-arrival time averaging

• Published in: Computer communications Vol. 29; no. 10; pp. 1696 - 1709
• Main Authors: Aweya, James, Montuno, Delfin Y., Ouellette, Michel, Felske, Kent
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 19.06.2006; Tokyo Elsevier Science; New York, NY
• Subjects: Applied sciences; Circuit emulation; Clock recovery; Clock synchronization; Computer science; control theory; systems; Computer systems and distributed systems. User interface; DCO; Digitally controlled oscillator; Exact sciences and technology; Jitter; Networks; Packet delay variation; Packet networks; Packet switching; PDV; Phase-locked loop; Software; TDM; Timing recovery; Clock synchronization; Digitally controlled oscillator; Timing recovery; DCO; Packet delay variation; Packet networks; PDV; Phase-locked loop; Jitter; TDM; Circuit emulation; Clock recovery; Averaging method; Packet switching; Correlation; Emulator; Case based reasoning; Synchronization; Timed system; Delay; Variance; Phase locked loop; Arrival time; Transmission loss
• ISSN: 0140-3664; 1873-703X
• DOI: 10.1016/j.comcom.2005.10.019

Accurate source clock recovery is an important element of circuit emulation services (CES) over packet networks. A well-known and widely implemented technique for clock recovery in CES is the one that is based on packet inter-arrival time (sometimes called time difference of arrival (TDOA)) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has not been fully characterized analytically in the literature. In this paper, we provide a full analytical examination of this well-known clock recovery technique. We analyze the effects of correlation of the PDV experienced by the constant bit rate (CBR) traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the PDV produces a large variance of the recovered clock. The paper also describes simple all-digital implementations of the clock recovery scheme using standard digitally controlled oscillators (DCOs).