A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 41; no. 6; pp. 1971 - 1975
• Main Authors: Cui, Lanlan, Liu, Xiaojian, Wu, Fei, Lu, Zhonghai, Xie, Changsheng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Binary system; Bit error rate; Bit-width; Codes; Complexity; Decoding; Decoding algorithm; Decoding performance; Economic and social effects; Error correcting codes; Error correction; Flash memory; Flash memory (computers); Hardware; Implementation complexity; Iterative decoding; Likelihood ratio; Log likelihood ratios (LLR); Low density parity check decoding; low-density parity-check (LDPC) codes; Manganese; Memory architecture; min-sum decoding; NAND circuits; NAND flash memory; Normalized min-sum algorithms; Quasi-cyclic LDPC (QC-LDPC); Reliability; Throughput; Uncorrectable bit error rates
• ISSN: 0278-0070; 1937-4151; 1937-4151
• DOI: 10.1109/TCAD.2021.3100273

For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve an attractive tradeoff between implementation complexity and decoding performance. In this article, a novel low-bit-width decoding scheme is introduced. In this scheme, the quasi-cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower uncorrectable bit error rate (UBER) with a negligible increase in computational complexity, especially with low-precision input log-likelihood ratio (LLR).