Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate

• Published in: Materials science & engineering. B, Solid-state materials for advanced technology Vol. 154; pp. 102 - 105
• Main Authors: Yoo, Ook Sang, Oh, Jungwoo, Kang, Chang Yong, Lee, Byoung Hun, Han, In Shik, Choi, Won-Ho, Kwon, Hyuk-Min, Na, Min-Ki, Majhi, Prashant, Tseng, Hsing-Huang, Jammy, Raj, Wang, Jin Suk, Lee, Hi-Deok
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 05.12.2008
• Subjects: Post-metallization annealing; Si capping; Surface passivation; Ge; Si capping; Surface passivation; Post-metallization annealing
• ISSN: 0921-5107; 1873-4944
• DOI: 10.1016/j.mseb.2008.06.031

We demonstrated the effect of post-metallization annealing and Si interlayer thickness on Ge MOS capacitor on Ge-on-Si substrate with HfO 2/TaN. Ge outdiffusion and oxygen interdiffusion were completely suppressed by thick Si interfacial layer. As a result, formation of insufficient low- k Ge oxides was effectively inhibited. It is confirmed that gate current of Si passivated Ge MOS was decreased by Si IL and decrease of gate current, J g is saturated after Si IL of 2 nm. It was also observed that when Si IL is thick enough to restrict Ge outdiffusion, increase of J g is not due to the temperature-induced Ge outdiffusion but due to the partial crystallization of HfO 2 at higher annealing temperature.