An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin

• Published in: IEEE journal of solid-state circuits Vol. 35; no. 11; pp. 1641 - 1647
• Main Authors: Pilo, H., Allen, A., Covino, J., Hansen, P.R., Lamphier, S., Murphy, C., Traver, T., Yee, P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuits; Clocks; CMOS; CMOS process; Consumption; Copper; Decoding; Driver circuits; Drivers; Frequency; High frequencies; Integrated circuit interconnections; Packaging; Random access memory; Static random access memory; Timing; Tracking systems
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.881210

This paper describes an 833-MHz 18-Mb CMOS SRAM with a 1.67-Gb/s/pin data rate. Issues that had to be overcome from previous-generation SRAMs to meet the performance goals are addressed. The SRAM has been successfully fabricated using a 0.18-/spl mu/m CMOS process with copper interconnects. It operates in two user-selectable double-data-rate modes (DDR and DDR2) and consumes 1.5 W of power at 833 MHz. In addition to the performance benefits resulting from this 0.18-/spl mu/m copper technology, architecture improvements, a data-to-echo-clock tracking system, and data symmetric output drivers made possible the high frequency of operation.