A Robust and Power-Efficient SoC Implementation in 65 nm
Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep...
Saved in:
Published in | Journal of computer science and technology Vol. 28; no. 4; pp. 682 - 688 |
---|---|
Main Author | |
Format | Journal Article |
Language | English |
Published |
Boston
Springer US
01.07.2013
Springer Nature B.V Loongson Technology Corporation Limited, Beijing 100190, China%Loongson Technology Corporation Limited, Beijing 100190, China%State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China Loongson Technology Corporation Limited, Beijing 100190, China State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China University of Chinese Academy of Sciences, Beijing 100049, China |
Subjects | |
Online Access | Get full text |
ISSN | 1000-9000 1860-4749 |
DOI | 10.1007/s11390-013-1368-7 |
Cover
Loading…
Summary: | Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design. |
---|---|
Bibliography: | Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design. 11-2296/TP Bin Xiao, Yi-Fu Zhang, Yan-Ping Gao, Liang Yang, Dong-Mei Wu, and Bao-Xia Fan( 1 State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China 2 University of Chinese Academy of Sciences, Beijing 100049, China 3 Loongson Technology Corporation Limited, Beijing 100190, China E-mail: {xiaobin01, zhangyifu, athene}@ict.ac.cn; yangliang@loongson.cn; {wudongmei, fanbaoxia}@ict.ac.cn) System-on-Chip, on-chip-variation, PVT detector, low power, hierarchical design flow ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 ObjectType-Article-2 ObjectType-Feature-1 content type line 23 |
ISSN: | 1000-9000 1860-4749 |
DOI: | 10.1007/s11390-013-1368-7 |