Deformation and interfacial sliding in back-end interconnect structures in microelectronic devices

• Published in: Journal of electronic materials Vol. 32; no. 10; pp. 1059 - 1071
• Main Authors: PARK, C, DUTTA, I, PETERSON, K. A, VELLA, J
• Format: Conference Proceeding Journal Article
• Language: English
• Published: New York, NY Institute of Electrical and Electronics Engineers 01.10.2003; Springer Nature B.V
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Thermal stress; interfacial sliding; Copper interconnects; Creep; Plastic deformation; Mismatching; thermal cycling; Thermal expansion; Interconnection; Electronic packaging; Integrated circuit; deformation; low-K dielectric; Copper; Reliability
• ISSN: 0361-5235; 1543-186X
• DOI: 10.1007/s11664-003-0089-z

Deformation of interconnect structures at the back-end of microelectronic devices during processing or service can have a pronounced effect on component reliability. Here, we use atomic force microscopy (AFM) to study plastic deformation and interfacial sliding of Cu interconnects on Si. The behavior of both standalone Cu lines and lines embedded in a low-K dielectric (LKD) was studied. Following thermal cycling, changes were observed in the in-plane JP) Cu line dimensions, as well as the out-of-plane (OOP) step height between Cu and the dielectric in single-layer structures. These were attributed to differential deformation of the Cu/Si and Cu/dielectric material pairs caused by thermal expansion mismatch, accommodated by interfacial creep. These results are discussed in light of previous work on the mechanism of interfacial creep. A simple shear-lag-based model, which may be used to estimate the extent of interfacial sliding, is proposed. Some experimental results on the distortion of Cu lines caused by package-level stresses following thermal cycling are also presented.