A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

• Published in: IEEE journal of solid-state circuits Vol. 51; no. 7; pp. 1630 - 1640
• Main Authors: Tharayil Narayanan, Aravind, Katsuragi, Makihiko, Kimura, Kento, Kondo, Satoshi, Tokgoz, Korkut Kaan, Nakata, Kengo, Wei Deng, Okada, Kenichi, Matsuzawa, Akira
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Chips (electronics); Circuit design; Circuits; CMOS; Delays; DTC; Dynamic range; fast locking; fractional-N synthesizer; Jitter; Linearity; Noise; Phase locked loops; Phase noise; phase-locked loop (PLL); pipelined phase interpolator; Power consumption; push-pull VCO; short-current free; sub-sampling PLL (SSPLL); Voltage-controlled oscillators; CMOS; DTC; short-current free; fast locking; sub-sampling PLL (SSPLL); fractional-N synthesizer; pipelined phase interpolator; push-pull VCO; phase-locked loop (PLL)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2016.2539344

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional-N PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional-N PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional-N mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.