Feature Indented Assertions for Analog and Mixed-Signal Validation

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 35; no. 11; pp. 1928 - 1941
• Main Authors: Ain, Antara, Bruto da Costa, Antonio Anastasio, Dasgupta, Pallab
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceptance criteria; Algorithm design and analysis; Algorithms; Analog and mixed-signal (AMS); assertions; Computer simulation; Design; Design analysis; Design criteria; Design engineering; Hardware design languages; Heuristic algorithms; Monitoring; Semantics; Settling; Syntactics; verification
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2016.2525798

The acceptance criteria for analog designs are traditionally defined in terms of real-valued features defined over behavioral responses. For example, rise time, peak overshoot, and settling time are features of the response of a second-order system under a step input. Designers of analog and mixed-signal (AMS) designs typically like to see whether the relevant features lie within their specified ranges, and if so, by what margin. Assertions are capable of capturing the acceptance criteria, but they do not help in evaluating how well (or by what margin) the design satisfies the specification. We introduce the notion of Feature Indented Assertions (FIAs) for overlaying the definition of real-valued features over the syntactic fabric of AMS assertions. In this paper, we present the formal syntax and semantics of our language, FIA, and demonstrate its ability to capture a wide variety of AMS features. We present our dynamic feature evaluation tool that plugs into standard AMS simulators through Verilog Procedural Interfaces and evaluates features over simulation. At the heart of this tool, we have our interval arithmetic-based algorithm for monitoring features over continuous time and value domains. This algorithm is presented with corresponding proofs of correctness and with results over industrial testcases.