An electromigration and thermal model of power wires for a priori high-level reliability prediction

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 12; no. 4; pp. 349 - 358
• Main Authors: Casu, M.R., Graziano, M., Masera, G., Piccinini, G., Zamboni, M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Countermeasures; Electromigration; Expenses; Fanout; Integrated circuit interconnections; Integrated circuit technology; Mathematical models; Power supplies; Power system interconnection; Power system modeling; Power system reliability; Predictive models; Projection; Very large scale integration; Wire; Wires
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2004.825599

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper.