Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

• Published in: IET circuits, devices & systems Vol. 11; no. 4; pp. 381 - 387
• Main Authors: Abdelrasoul, Maher, Sayed, Mohammed S, Goulart, Victor
• Format: Journal Article
• Language: English
• Published: Stevenage The Institution of Engineering and Technology 01.07.2017; John Wiley & Sons, Inc
• Subjects: Algorithms; Circuits; CMOS; CMOS integrated circuits; codecs; Coding standards; DCT; Discrete cosine transform; discrete cosine transforms; HEVC; high efficiency video coding encoder; Image coding; inverse discrete cosine transform; inverse transforms; Multimedia; Process controls; Process variables; Prototyping; Quality standards; real-time processing; Research Article; size 65 nm; video coding; Video compression; video sequences; discrete cosine transforms; size 65 nm; codecs; video coding; HEVC; inverse transforms; high efficiency video coding encoder; CMOS; DCT; real-time processing; video sequences; CMOS integrated circuits; inverse discrete cosine transform
• ISSN: 1751-858X; 1751-8598; 1751-8598
• DOI: 10.1049/iet-cds.2016.0423

In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT.