High throughput fault-resilient AES architecture

• Published in: Chronic diseases and translational medicine Vol. 13; no. 4; pp. 312 - 323
• Main Authors: Sheikhpour, Saeide, Mahani, Ali, Bagheri, Nasour
• Format: Journal Article
• Language: English
• Published: Beijing The Institution of Engineering and Technology 01.07.2019; John Wiley & Sons, Inc
• Subjects: advanced encryption standard; block cipher; confidential information; critical applications; cryptographic algorithms; cryptography; Data encryption; effective attacks; Embedded systems; equivalent blocks; Error correction & detection; error detection; fault injection attack; fault resilient AES architecture; Field programmable gate arrays; high‐error detection rate; inexpensive requirement; lightweight error detection architecture; malicious attacks; Number systems; parallel AES architecture; private information; Research Article; split each block; inexpensive requirement; lightweight error detection architecture; block cipher; confidential information; malicious attacks; advanced encryption standard; high-error detection rate; private information; fault resilient AES architecture; cryptography; error detection; effective attacks; equivalent blocks; split each block; parallel AES architecture; cryptographic algorithms; fault injection attack; critical applications
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2018.5083

As more and more confidential information is being transmitted securely, the use of cryptographic algorithms is expanded. However, existing cryptographic algorithms are subject to various malicious attacks. Fault injection attack is one of the most effective attacks that are able to extract private information with the inexpensive requirement and short amount of time. AES is a block cipher that is used in many critical applications. Here, a lightweight error-detection architecture for AES has been proposed; the authors call it as high throughput fault-resilient AES (HFA). In the proposed architecture, the authors use parallel AES architecture, which contains four equivalent blocks and split each block into two pipeline stages. The authors have shown that HFA achieves high error-detection rate while keeping overheads reasonable.