Time Delay Integration and In-Pixel Spatiotemporal Filtering Using a Nanoscale Digital CMOS Focal Plane Readout

• Published in: IEEE transactions on electron devices Vol. 56; no. 11; pp. 2516 - 2523
• Main Authors: Tyrrell, B., Anderson, K., Baker, J., Berger, R., Brown, M., Colonero, C., Costa, J., Holford, B., Kelly, M., Ringdahl, E., Schultz, K., Wey, J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Architecture; Arrays; Detectors; Digital; Focal plane; Image processing; imaging; infrared image sensors; infrared surveillance; infrared tracking; Nanostructure; Noise; Pixel; Pixels; Power dissipation; Radiation detectors; Registers
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2009.2030719

A digital focal plane array (DFPA) architecture has been developed that incorporates per-pixel full-dynamic-range analog-to-digital conversion and orthogonal-transfer-based realtime digital signal processing capability. Several long-wave infrared-optimized pixel processing focal plane readout integrated circuit (ROIC) designs have been implemented, each accommodating a 256 times 256 30-mum-pitch detector array. Demonstrated in this paper is the application of this DFPA ROIC architecture to problems of background pedestal mitigation, wide-field imaging, image stabilization, edge detection, and velocimetry. The DFPA architecture is reviewed, and pixel performance metrics are discussed in the context of the application examples. The measured data reported here are for DFPA ROICs implemented in 90-nm CMOS technology and hybridized to Hg x Cd 1-x Te (MCT) detector arrays with cutoff wavelengths ranging from 7 to 14.5 mum and a specified operating temperature of 60 K-80 K.