A 65-nm CMOS Lossless Bio-Signal Compression Circuit With 250 FemtoJoule Performance Per Bit

• Published in: IEEE transactions on biomedical circuits and systems Vol. 13; no. 5; pp. 1087 - 1100
• Main Authors: Crispin-Bailey, Christopher, Dai, Chenglaing, Austin, Jim
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.10.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Biomedical measurement; Circuit design; CMOS; Compression; Compression algorithms; Compression ratio; Compression tests; Data Compression; Data storage; Data transmission; ECG; EEG; Encoding; Energy conversion efficiency; Gating; Hardware; Humans; Integrated circuits; lossless data compression; Optimization; power efficiency; Signal Processing, Computer-Assisted; Storage capacity; Very large scale integration; VLSI design; wearable sensors

A 65 nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel `xor-log2-sub-band' data compression scheme is evaluated, achieving modest...