A 65-nm CMOS Lossless Bio-Signal Compression Circuit With 250 FemtoJoule Performance Per Bit

A 65 nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel `xor-log2-sub-band' data compression scheme is evaluated, achieving modest...

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Bibliographic Details
Published inIEEE transactions on biomedical circuits and systems Vol. 13; no. 5; pp. 1087 - 1100
Main Authors Crispin-Bailey, Christopher, Dai, Chenglaing, Austin, Jim
Format Journal Article
LanguageEnglish
Published United States IEEE 01.10.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Algorithms
Biomedical measurement
Circuit design
CMOS
Compression
Compression algorithms
Compression ratio
Compression tests
Data Compression
Data storage
Data transmission
ECG
EEG
Encoding
Energy conversion efficiency
Gating
Hardware
Humans
Integrated circuits
lossless data compression
Optimization
power efficiency
Signal Processing, Computer-Assisted
Storage capacity
Very large scale integration
VLSI design
wearable sensors
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Summary:A 65 nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel `xor-log2-sub-band' data compression scheme is evaluated, achieving modest compression, but with very low resource cost. With the intent to design the 'simplest useful compression algorithm', the outcome is demonstrated to be very favourable where power must be saved by trading off compression effort against data storage capacity, or data transmission power, even where more complex algorithms can deliver higher compression ratios. A VLSI design and fabricated Integrated Circuit implementation are presented, and estimated performance gains and efficiency measures for various bio-medical use-cases are given. Power costs as low as 1.2 pJ per sample-bit are suggested for a 10 kSa/s data-rate, whilst utilizing a power-gating scenario, and dropping to 250 fJ/bit at continuous conversion data-rates of 5 MSa/sec. This is achieved with a diminutive circuit area of 155 um 2 . Both power and area appear to be state-of-the-art in terms of compression versus resource cost, and this yields benefit for system optimization.
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ISSN:1932-4545
1940-9990
DOI:10.1109/TBCAS.2019.2938672