A new approach to built-in self-testable datapath synthesis based on integer linear programming

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 8; no. 5; pp. 594 - 605
• Main Authors: Han Bin Kim, Dong Sam Ha, Takahashi, T., Yamaguchi, T.J.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Piscataway, NJ IEEE 01.10.2000; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Built-in self-test; Circuit synthesis; Circuit testing; Circuits; Design engineering; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Flow graphs; High level synthesis; Integer linear programming; Integrated circuit interconnections; Integrated circuits; Linear programming; Logic design; Logic programming; Methods; Optimization; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; Synthesis; Tasks; Test times; Integer programming; Integrated circuit; Linear programming; Design for testability; High level synthesis; Built in self test; Optimal design
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/92.894164

The focus of high-level built-in self-test (BIST) synthesis is register assignment, which involves system register assignment, BIST register assignment, and interconnection assignment. To reduce the complexity involved in the assignment process, existing high-level BIST synthesis methods decouple the three tasks and perform the tasks sequentially at the cost of global optimality. They also try to achieve only one objective: minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we propose a new approach to the BIST data path synthesis based on integer linear programming that performs the three register assignment tasks concurrently to yield optimal designs. In addition, our approach finds an optimal register assignment for each k-test session. Therefore, it offers a range of designs with different figures of merit in area and test time. Our experimental results show that our method successfully synthesizes a BIST circuit for every k-test session for all six circuits experimented. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods.