A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 63; no. 3; pp. 229 - 233
• Main Authors: Tretter, Gregor, Fritsche, David, Khafaji, Mohammad Mahdi, Carta, Corrado, Ellinger, Frank
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplification; Amplitudes; Bandwidth; Circuits; CMOS; CMOS integrated circuits; Corners; Gain; Harmonic distortion; highspeed sampling; Impedance matching; Inductors; Manganese; Power consumption; sampling circuit; switched-capacitor; time interleaving; track-and-hold amplifier; switched capacitor (SC); sampling circuit; High-speed sampling; time interleaving; track-and-hold amplifier (THA)
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2015.2503579

This brief presents a 25-GS/s track-and-hold amplifier (THA) implemented in a 28-nm low-power digital CMOS process. Given the intrinsic low-pass behavior of the THA core, a frequency compensation technique is employed to improve the bandwidth by increasing the input amplitude for higher frequencies. This enhances the small-signal bandwidth by almost 30% to 70 GHz. Large-signal measurements show a 3-dB corner frequency of 55 GHz, which enables a performance sufficient for time-interleaved analog-to-digital converter systems operating above 100 GS/s. At a peak-to-peak input amplitude of 400 mV, the total harmonic distortion is -32 dB for a 50-GHz input signal at a dc power consumption of 73 mW.